1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of eliminating floating body effects in the fabrication of a silicon-on-insulator (SOI) MOSFET in the fabrication of integrated circuits.
2. Description of the Prior Art
An isolation technology that depends on completely surrounding devices by an insulator is referred to as silicon-on-insulator (SOI) technology. In general, the advantages of SOI technology include simple fabrication sequence, reduced capacitive coupling between circuit elements, and increased packing density. The SOI technology is discussed in Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 66–67. A disadvantage of SOI technology is inherent floating body effects due to the limitation in incorporating effective contact to the body. In bulk silicon MOSFETs, the bottom of the bulk silicon can be connected to a fixed potential. However, in an SOI MOSFET, the body is electrically isolated from the bottom of the substrate. The floating body effects result in drain current “kink” effect, abnormal threshold slope, low drain breakdown voltage, drain current transients, and noise overshoot. The “kink” effect originates from impact ionization. When an SOI MOSFET is operated at a large drain-to-source voltage, channel electrons cause impact ionization near the drain end of the channel. Holes build up in the body of the device, raising body potential and thereby raising threshold voltage. This increases the MOSFET current causing a “kink” in the current vs. voltage (I–V) curves. It is desired to eliminate floating body effects.
A number of patents present a variety of isolation methods for silicon-on-insulator and other types of MOSFETs. U.S. Pat. No. 5,504,033 to Bajor et al shows a process for forming both deep and shallow trenches in a SOI device; however, there is no requirement for the trenches to contact the substrate. U.S. Pat. No. 6,063,652 to Kim and U.S. Pat. No. 5,591,650 to Hsu et al show an SOI device having a shallow trench isolation (STI) formed entirely through the silicon to the oxide layer. U.S. Pat. No. 5,874,328 to Liu et al discloses trench isolation through a source/drain region. U.S. Pat. No. 5,674,760 to Hong discloses an isolation structure, but not in SOI technology. U.S. Pat. No. 5,930,605 to Mistry et al discloses a Schottky diode connection between the body and one of the source/drain regions.